The present invention relates, in general, to the field of integrated circuit (IC) memory devices. More particularly, the present invention relates to a limited output address register technique providing selectively variable write latency in double data rate 2 (DDR2) integrated circuit memory devices.
DDR2 is a recently defined JEDEC (Joint Electronic Device Engineering Council) memory standard published in January, 2004 as JESD79-2A which is a follow on to the DDR1 memory specification. The DDR2 standard specifies a number of improvements over that of the DDR1 standard which serve to make the new memory types more efficient, both at transferring data and at saving power. In addition to built in On Die Termination (ODT), posted column address strobe (CAS) and additive latency (AL) features are two new features which enable the memory to run faster and more efficiently.
With posted CAS and additive latency, a READ or WRITE command can be issued immediately after the ACTIVATE command, then this READ/WRITE command is delayed internally by a predetermined number of clock cycles (hence additive latency) before being executed.
The JEDEC definition of DDR2 allows for CAS latencies of 3, 4 or 5, as compared to DDR1's 1.5, 2 and 2.5. Write latency is also considerably greater with DDR2. While DDR1 allows a single cycle for write latency, DDR2 defines write latency as equal to the read latency minus one (WL=RL−1), where the read latency is equal to the additive latency (AL) plus the /CAS latency (CL) (or RL=AL+CL). This provides a time profile for both READ and WRITE transactions that enables easier pipelining of the two transaction types, and thus higher bus utilization.